For many applications, and particularly in consumer electronic devices, the large and heavy cathode ray tube (CRT) has been replaced by flat panel display types such as liquid crystal display (LCD), plasma, and organic light emitting diode (OLED). A flat panel display contains an array of display elements. Each display element is to receive a signal that represents the picture element (pixel) value to be displayed at that location. In an active matrix array, the pixel signal is applied using a pixel transistor that is coupled to and integrated with the display element. The pixel transistor acts as a switch element. It has a carrier electrode that receives the pixel signal and a control electrode that receives a gate (select) signal. The gate signal may serve to turn on or turn off the transistor so as to selectively apply or “sample” the pixel signal onto the coupled display element. In many instance, the pixel transistor is formed as a thin film transistor (TFT) on the display panel as its substrate.
Typically, thousands or millions of copies of the display element and its associated switch element (e.g., an LCD cell and its associated field effect transistor, FET) are reproduced in the form of an array, on a substrate such as a plane of glass (in the case of an LCD panel) or other suitable substrate for the display elements. The array is overlaid with a grid of data lines and gate lines. The data lines serve to deliver the pixel signals to the carrier electrodes of the transistors and the gate lines serve to apply the gate signals to the control electrodes of the transistors. In other words, each of the data lines is coupled to a respective group of display elements, typically referred to as a column of display elements, while each of the gate lines is coupled to a respective row of display elements.
Each data line is coupled to a data line driver circuit that receives control and pixel signals from a signal generator. The latter translates incoming pixel values (for example, red, green and blue pixel values) into data signals (with appropriate timing). The data line driver then performs the needed voltage level shifting to produce a pixel signal with the needed fan-out (current capability).
As to the gate lines, these are coupled to a gate driver that receives clock (control) signals and a start pulse signal from the signal generator. The clock control and start pulse signals may be generated by display driver circuitry, based on horizontal and vertical sync signals that help define the scan of each frame to be displayed. The array of display elements are, in most cases, driven in a horizontal or line-by-line scanning fashion: the desired pixel signals for a selected line or row of display elements are provided on the data lines, and the pixel signals are then “written” into a selected row of display elements when a pulse is asserted on the gate line that is connected to the pixel transistors of the selected row, by the gate driver. The approach is to scan line-by-line or row-by-row in a vertical direction, until the entire display element array has been “filled” with the pixel values of a single image frame. For this purpose, the gate driver is designed to act as a shift register so that each time a start pulse is received by the gate driver, a shift register circuit starts and propagates an output pulse. The outputs of the shift register circuit are connected to level shifting output stages, which in turn are connected to the gate lines. Thus, the gate driver sequentially drives the pixel transistors on each gate line (with the needed fan out and voltage swing).